Design methodology for general enhancement of a single-stage self-compensated folded-cascode operational transconductance amplifiers in 65 nm CMOS process

The problems resulting from the use of nano-MOSFETs in design operational trans-conductance amplifiers (OTAs) lead to an urgent need for new techniques produce high-performance metrics OTAs suitable very high-frequency applications. In this paper, enhancement and equations proposed single-stage folded-cascode (FCOTA) are presented its various performance metrics. FCOTA adopts (FC) current sources with cascode mirrors (CCMs) load. Using 65 nm complementary metal-oxide semiconductor (CMOS) process predictive technology model (PTM), HSPICE2019-based simulation results show that designed can achieve a high open-loop differential-mode DC voltage gain 65.64 dB, unity-gain bandwidth 263 MHz, stability phase-margin 73°, low power dissipation 0.97 mW, input-offset 0.14 uV, swing-output voltages −0.97 0.91 V, equivalent input-referred noise 15.8 nV/Hz, common-mode rejection ratio 190.64 positive/negative slew-rates 157.5/58.3 V⁄us, fast settling-time 5.1 ns, extension input range −0.44to 1 power-supply ratios 75.5/68.8 dB. values small/large-signal figures-of-merits (